FIG. 1 illustrates a prior art computer system 10 that includes a prior video processing system 12 connected to a bus 14 of computer system 10 via a buffer 13. Video processing system 12 receives analog video data from an external video camera (not shown) and then converts and decodes the video data in a converter 12a and a decoder 12b. The processed digital video data are then applied to a scaling circuit 12c for scaling down the video image. The scaled data are then applied to a display 18 via bus 14 for display or to a memory (e.g., memory 17) via bus 14 for storage before being displayed on display 18.
In a prior video processing and communication system such as system 12 as shown in FIG. 1, spatial down-scaling of a digital video image is typically accomplished by passing the image data through a low pass filter and subsampling the resulting data. Storage elements are typically required for the filtering as multiple input samples, or taps, are combined to generate one output sample during the filtering operation. The total amount of storage or memory required depends on the number of desired filter taps and the ordering of the input data. As an example, the amount of memory required for vertical scaling of a video image can be substantial because pixels usually arrive in raster order. This typically causes an entire line of horizontal pixels to be buffered between each pair of vertically adjacent pixels.
When the scaled video image data are then delivered to display 18 or memory 17 via bus 14, a memory configured as a FIFO (First-in-First-Out) buffer 13 is typically required. FIFO buffer 13 is used to buffer the data before they are sent to bus 14. This is because bus 14 may be engaged in data transfer between other devices connected also to bus 14 when the scaled video image data are available for transmission by bus 14. When this occurs, the scaled video image data need to be buffered until bus 14 becomes available to transmit the data. The time period from the time the scaled data are available for transmission but bus 14 is not available to the time bus 14 is available for transmission of the scaled data is typically referred to as the latency period. As is known, the amount of buffering required for the scaled data is typically determined by the duration of the latency period and the incoming data rate. Systems with high latency periods or high data transfer rates typically require large latency FIFO buffers.
Therefore, in a system that requires a data stream to be both down-scaled and delivered to a shared resource (e.g., bus), memory is typically required to buffer or store the data for the scaling operation. In addition, memory is also required for delivering the scaled data to the shared resource when the shared resource has an access latency. This means that the two functions are implemented with redundant memory. The redundant memory typically increases the memory cost of the system, which in turn increases the system cost.